; Adding AtMega8 and option support ; Added AtTiny24,AtTiny15,AtTiny12,AtTiny11 psEEROMBASE equ $100000 ; The ParaSys Driver puts it here. . . psFUSEBASE equ $200000 ; The ParaSys Driver puts them here. . . psOPTIONBASE equ $300000 ; The ParaSys Driver puts them here. . . ; Setup defaults for the vectors if def Start vStart equ Start else vStart equ EOIVaddr endif if def irqSpurious virqSpurious equ irqSpurious else virqSpurious equ EOIVaddr endif ; AtTiny24, 44 and 84 if CPU_NAME ="ATTINY24" optDevTypeByte = $11 ; ATTINY24 device ID for the programmer AVRTINY24_SET equ true ; Use the common equates RAMSIZE equ $080 ; Size of SRAM EEROMSIZE equ $080 ; Size of EEROM FLASHLENGTH equ $800 ; Size of FLASH endif if CPU_NAME ="ATTINY44" optDevTypeByte = $12 ; ATTINY44 device ID for the programmer AVRTINY24_SET equ true ; Use the common equates RAMSIZE equ $100 ; Size of SRAM EEROMSIZE equ $100 ; Size of EEROM FLASHLENGTH equ $1000 ; Size of FLASH endif if CPU_NAME ="ATTINY84" optDevTypeByte = $13 ; ATTINY84 device ID for the programmer AVRTINY24_SET equ true ; Use the common equates RAMSIZE equ $200 ; Size of SRAM EEROMSIZE equ $200 ; Size of EEROM FLASHLENGTH equ $2000 ; Size of FLASH endif if def AVRTINY24_SET ; ***** I/O Register Definitions org AVR_IO_BASE ; IO port addressing mode PPR ds 1 ; ($00) DIDR0 ds 1 ; ds 1 ; ADCSRB ds 1 ; ADCL ds 1 ; ADCH ds 1 ; ADCSRA ds 1 ; ADMUX ds 1 ; ACSR ds 1 ; ($08) ds 1 ; ds 1 ; TIFR1 ds 1 ; TIMSK1 ds 1 ; USICR ds 1 ; USISR ds 1 ; USIDR ds 1 ; USIBR ds 1 ; ($10) ds 1 ; PCMSK0 ds 1 ; GPIOR0 ds 1 ; GPIOR1 ds 1 ; GPIOR2 ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; PINA ds 1 ; DDRA ds 1 ; PORTA ds 1 ; EECR ds 1 ; EEDR ds 1 ; EEARL ds 1 ; EEARH ds 1 ; PCMSK1 ds 1 ; ($20) WDTCSR ds 1 ; TCCR1C ds 1 ; GTCCR ds 1 ; ICR1L ds 1 ; ICR1H ds 1 ; CLKPR ds 1 ; DWDR ds 1 ; OCR1BL ds 1 ; OCR1BH ds 1 ; OCR1AL ds 1 ; OCR1AH ds 1 ; TCNT1L ds 1 ; TCNT1H ds 1 ; TCCR1B ds 1 ; TCCR1A ds 1 ; TCCR0A ds 1 ; ($30) OSCCAL ds 1 ; TCNT0 ds 1 ; TCCR0B ds 1 ; MCUSR ds 1 ; MCUCR ds 1 ; OCR0A ds 1 ; SPMCSR ds 1 ; TIFR0 ds 1 ; TIMSK0 ds 1 ; GIFR ds 1 ; GIMSK ds 1 ; OCR0B ds 1 ; SPL ds 1 ; SPH ds 1 ; SREG ds 1 ; ; IRQ enable bits, etc UNCHECKED !!! ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK ; Flags bTOV0 =$01 ; ; Registers al reg r16 ; ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; org $60 RAMSTART ds RAMSIZE ; Adjust for registers and I/O RAMEND equ *-1 ; Last byte FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and $0F) + ((fsSUT and $03)<<4) ; Handle CKOUT. True is enabled... if def fsCKOUT if fsCKOUT fsFuseLowT2 = fsFuseLowT1 ; Low is enabled else fsFuseLowT2 = fsFuseLowT1 or $40 ; High is disabled endif else fsFuseLowT2 = fsFuseLowT1 or $40 ; High is disabled endif ; Handle CKDIV8. True is enabled... if def fsCKDIV8 if fsCKDIV8 fsFuseLow = fsFuseLowT2 ; Low is enabled else fsFuseLow = fsFuseLowT2 or $80 ; High is disabled endif else fsFuseLow = fsFuseLowT2 or $80 ; High is disabled endif ; Fuse High fsFuseHighEn = 1 if def fsBOD fsFHT1 = %1 1 0 1 1 or (fsBOD and $07) else fsFHT1 = %1 1 0 1 1 111 endif if def fsEESAVE fsFHT2 = fsFHT1 and %1 1 1 1 0 111 else fsFHT2 = fsFHT1 endif if def fsWDTFORCE fsFHT3 = fsFHT2 and %1 1 1 0 1 111 else fsFHT3 = fsFHT2 endif if def fsDWEN fsFHT4 = fsFHT3 and %1 0 1 1 1 111 ; Enable it? else fsFHT4 = fsFHT3 endif if def fsRESET_DISABLE fsFHT5 = fsFHT4 and %0 1 1 1 1 111 ; Disable it else fsFHT5 = fsFHT4 or (1<<7) endif fsFuseHigh = fsFHT5 ; Fuse Extended fsFuseExtEn = 1 if def fsSELFPRGEN if fsSELFPRGEN fsFuseExt = $FF else fsFuseExt = $FE endif else fsFuseExt = $FF endif ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif else fsFuseLowEn = 0 ; Don't drive the fuses fsFuseLow = 0 fsFuseHighEn = 0 fsFuseHigh = 0 fsFuseExtEn = 0 fsFuseExt = 0 endif ; Interrupt vectors org 0 RESETaddr ds 2 ; RESET EXT_INT0addr ds 2 ; External Interrupt0 Vector Address PCINT0addr ds 2 ; Pin change 0 interrupt PCINT1addr ds 2 ; Pin change 1 interrupt WATCHDOGaddr ds 2 ; Watchdog interrupt TMR1CAPTaddr ds 2 ; Timer 1 Capture TMR1COMPA ds 2 ; Timer 1 Compare A TMR1COMPB ds 2 ; Timer 1 Compare B TMR1OVRaddr ds 2 ; Timer 1 Overflow TMR0COMPA ds 2 ; Timer 0 Compare A TMR0COMPB ds 2 ; Timer 0 Compare B TMR0OVRaddr ds 2 ; Timer 0 Overflow ANACOMPaddr ds 2 ; Analog Comparator ADCaddr ds 2 ; ADC EERDYaddr ds 2 ; EEROM ready USI_STRaddr ds 2 ; USI Start USI_OVRaddr ds 2 ; USI Overflow EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here rjmp vStart ; Reset Vector if def irqEI0 rjmp irqEI0 ; Use the defined one else rjmp virqSpurious ; endif if def irqPINC0 rjmp irqPINC0 ; Use the defined one else rjmp virqSpurious ; endif if def irqPINC1 rjmp irqPINC1 ; Use the defined one else rjmp virqSpurious ; endif if def irqWATCHDOG rjmp irqWATCHDOG ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR1CAPT rjmp irqTMR1CAPT ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR1COMPA rjmp irqTMR1COMPA ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR1COMPB rjmp irqTMR1COMPB ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR1OVR rjmp irqTMR1OVR ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR0COMPA rjmp irqTMR0COMPA ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR0COMPB rjmp irqTMR0COMPB ; Use the defined one else rjmp virqSpurious ; endif if def irqTMR0OVR rjmp irqTMR0OVR ; Use the defined one else rjmp virqSpurious ; endif if def irqANACOMP rjmp irqANACOMP ; Use the defined one else rjmp virqSpurious ; endif if def irqADC rjmp irqADC ; Use the defined one else rjmp virqSpurious ; endif if def irqEERDY rjmp irqEERDY ; Use the defined one else rjmp virqSpurious ; endif if def irqUSI_STR rjmp irqUSI_STR ; Use the defined one else rjmp virqSpurious ; endif if def irqUSI_OVR rjmp irqUSI_OVR ; Use the defined one else rjmp virqSpurious ; endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtTiny24 ; AtTiny11 if CPU_NAME ="ATTINY11" optDevTypeByte = $0C ; Device ID for the programmer ; ***** I/O Register Definitions org $00 ; IO port addressing mode setiooffset $00 ; This subtracts $00 from addresses in IO ; instructions. ds 1 ; ($00) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ACSR ds 1 ; ($08) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($10) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($20) WDTCR ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($30) ds 1 ; TCNT0 ds 1 ; TCCR0 ds 1 ; MCUSR ds 1 ; MCUCR ds 1 ; ds 1 ; ds 1 ; TIFR ds 1 ; TIMSK ds 1 ; GIFR ds 1 ; GIMSK ds 1 ; ds 1 ; ds 1 ; ds 1 ; SREG ds 1 ; ; IRQ enable bits, etc UNCHECKED !!! ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK ; Flags bTOV0 =$01 ; ; Registers al reg r16 ; ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $000 ; We have no SRAM FLASHLENGTH equ $400 ; Size of FLASH FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. These are the new definitions of the fuse control. . . 19/11/2004 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 if def fsClockSrc fsFuseLowT1 = (fsClockSrc and $07) ; Three bits else fsFuseLowT1 = %100 ; Default to internal osc endif if fsFuseLowT1 <> %100 zeuserror "Check the clock options!" endif if not def fsRESET_DISABLE ; True = fuse programmed fsFuseLowT2 = fsFuseLowT1 or $08 ; High is reset enabled else ; We have a reset disable. if fsRESET_DISABLE fsFuseLowT2 = fsFuseLowT1 ; Disabled else fsFuseLowT2 = fsFuseLowT1 or $08 ; Not disabled endif endif if not def fsFAST_START ; True = fuse programmed fsFuseLowT3 = fsFuseLowT2 or $10 ; High is Normal else ; We have a reset disable. if fsFAST_START fsFuseLowT3 = fsFuseLowT2 ; Disabled else fsFuseLowT3 = fsFuseLowT2 or $10 ; Not disabled endif endif fsFuseLow = fsFuseLowT3 or %111 0 0 000 ; Force the unused one's high ; We don't have high or extended fuse byte fsFuseHighEn = 0 ; Turn these off by default fsFuseHigh = 0 ; fsFuseExtEn = 0 ; Turn these off by default fsFuseExt = 0 ; ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif endif ; Interrupt vectors org 0 RESETaddr ds 2 ; RESET INT0addr ds 2 ; External Interrupt0 Vector Address PINCaddr ds 2 ; Pin change interrupt TMR0OVRaddr ds 2 ; Timer 0 Overflow ANACOMPaddr ds 2 ; Analog Comparator EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here rjmp vStart ; Reset Vector if def irqEI0 rjmp irqEI0 ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqPINC rjmp irqPINC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR rjmp irqTMR0OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANACOMP rjmp irqANACOMP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtTiny11 ; AtTiny12 if CPU_NAME ="ATTINY12" optDevTypeByte = $0D ; Device ID for the programmer ; ***** I/O Register Definitions org $00 ; IO port addressing mode setiooffset $00 ; This subtracts $00 from addresses in IO ; instructions. ds 1 ; ($00) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ACSR ds 1 ; ($08) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($10) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; ds 1 ; ds 1 ; ds 1 ; EECR ds 1 ; EEDR ds 1 ; EEAR ds 1 ; ds 1 ; ds 1 ; ($20) WDTCR ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($30) OSCCAL ds 1 ; TCNT0 ds 1 ; TCCR0 ds 1 ; MCUSR ds 1 ; MCUCR ds 1 ; ds 1 ; ds 1 ; TIFR ds 1 ; TIMSK ds 1 ; GIFR ds 1 ; GIMSK ds 1 ; ds 1 ; ds 1 ; ds 1 ; SREG ds 1 ; ; IRQ enable bits, etc UNCHECKED !!! ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK ; Flags bTOV0 =$01 ; ; Registers al reg r16 ; ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $000 ; Size of SRAM EEROMSIZE equ $40 ; Size of EEROM ; org $60 ;RAMSTART ds RAMSIZE ; Adjust for registers and I/O ;RAMEND equ *-1 ; Last byte FLASHLENGTH equ $400 ; Size of FLASH FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. These are the new definitions of the fuse control. . . 10/12/2003 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and $0F) if not def fsBOD fsFuseLowT2 = fsFuseLowT1 or $C0 ; High is disabled else ; We have a BOD. What level? 0 = low if fsBOD=0 fsFuseLowT2 = fsFuseLowT1 or $80 ; Low else fsFuseLowT2 = fsFuseLowT1 ; High endif endif if not def fsRESET_DISABLE fsFuseLow = fsFuseLowT2 or $10 ; High is reset enabled else ; We have a reset disable. if fsRESET_DISABLE fsFuseLow = fsFuseLowT2 ; Disabled else fsFuseLow = fsFuseLowT2 or $10 ; Not disabled endif endif ; We don't have high or extended fuse byte fsFuseHighEn = 0 ; Turn these off by default fsFuseHigh = 0 ; fsFuseExtEn = 0 ; Turn these off by default fsFuseExt = 0 ; ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif endif ; Interrupt vectors org 0 RESETaddr ds 2 ; RESET INT0addr ds 2 ; External Interrupt0 Vector Address PINCaddr ds 2 ; Pin change interrupt TMR0OVRaddr ds 2 ; Timer 0 Overflow EERDYaddr ds 2 ; EEROM ready ANACOMPaddr ds 2 ; Analog Comparator EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here rjmp vStart ; Reset Vector if def irqEI0 rjmp irqEI0 ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqPINC rjmp irqPINC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR rjmp irqTMR0OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEERDY rjmp irqEERDY ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANACOMP rjmp irqANACOMP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtTiny12 ; AtTiny15 if CPU_NAME ="ATTINY15" optDevTypeByte = $10 ; Device ID for the programmer ; ***** I/O Register Definitions org $00 ; IO port addressing mode setiooffset $00 ; This subtracts $00 from addresses in IO ; instructions. ds 1 ; ($00) ds 1 ; ds 1 ; ds 1 ; ADCL ds 1 ; ADCH ds 1 ; ADCSR ds 1 ; ADMUX ds 1 ; ACSR ds 1 ; ($08) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ($10) ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; ds 1 ; ds 1 ; ds 1 ; EECR ds 1 ; EEDR ds 1 ; EEAR ds 1 ; ds 1 ; ds 1 ; ($20) WDTCR ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; ds 1 ; SFIOR ds 1 ; OCR1B ds 1 ; OCR1A ds 1 ; TCNT1 ds 1 ; TCCR1 ds 1 ; ($30) OSCCAL ds 1 ; TCNT0 ds 1 ; TCCR0 ds 1 ; MCUSR ds 1 ; MCUCR ds 1 ; ds 1 ; ds 1 ; TIFR ds 1 ; TIMSK ds 1 ; GIFR ds 1 ; GIMSK ds 1 ; ds 1 ; ds 1 ; ds 1 ; SREG ds 1 ; ; IRQ enable bits, etc UNCHECKED !!! ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK ; Flags bTOV0 =$01 ; ; Registers al reg r16 ; ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $000 ; Size of SRAM EEROMSIZE equ $40 ; Size of EEROM ; org $60 ;RAMSTART ds RAMSIZE ; Adjust for registers and I/O ;RAMEND equ *-1 ; Last byte FLASHLENGTH equ $400 ; Size of FLASH FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. These are the new definitions of the fuse control. . . 10/12/2003 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and %0000 00 11) or %0000 11 00 if not def fsBOD fsFuseLowT2 = fsFuseLowT1 or $C0 ; High is disabled else ; We have a BOD. What level? 0 = low if fsBOD=0 fsFuseLowT2 = fsFuseLowT1 or $80 ; Low else fsFuseLowT2 = fsFuseLowT1 ; High endif endif if not def fsRESET_DISABLE fsFuseLow = fsFuseLowT2 or $10 ; High is reset enabled else ; We have a reset disable. if fsRESET_DISABLE fsFuseLow = fsFuseLowT2 ; Disabled else fsFuseLow = fsFuseLowT2 or $10 ; Not disabled endif endif ; We don't have high or extended fuse byte fsFuseHighEn = 0 ; Turn these off by default fsFuseHigh = 0 ; fsFuseExtEn = 0 ; Turn these off by default fsFuseExt = 0 ; ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif endif ; Interrupt vectors org 0 RESETaddr ds 2 ; RESET INT0addr ds 2 ; External Interrupt0 Vector Address PINCaddr ds 2 ; Pin change interrupt TMR1CMPaddr ds 2 ; Timer 1 Compare TMR1OVRaddr ds 2 ; Timer 1 Overflow TMR0OVRaddr ds 2 ; Timer 0 Overflow EERDYaddr ds 2 ; EEROM ready ANACOMPaddr ds 2 ; Analog Comparator ADCaddr ds 2 ; ADC Comparator EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here rjmp vStart ; Reset Vector if def irqEI0 rjmp irqEI0 ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqPINC rjmp irqPINC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1CMP rjmp irqTMR1CMP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1OVR rjmp irqTMR1OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR rjmp irqTMR0OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEERDY rjmp irqEERDY ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANACOMP rjmp irqANACOMP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqADC rjmp irqADC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtTiny15 ; AtMega8 if CPU_NAME ="ATMEGA8" optDevTypeByte = $07 ; Device ID for the programmer ; ***** I/O Register Definitions org $20 ; IO port addressing mode setiooffset $20 ; This subtracts $20 from addresses in IO ; instructions. TWBR ds 1 ; ($20) TWSR ds 1 ; TWAR ds 1 ; TWDR ds 1 ; ADCL ds 1 ; ADCH ds 1 ; ADCSRA ds 1 ; ADMUX ds 1 ; ACSR ds 1 ; UBRR0L ds 1 ; UCSR0B ds 1 ; UCSR0A ds 1 ; UDR0 ds 1 ; SPCR ds 1 ; SPSR ds 1 ; SPDR ds 1 ; PIND ds 1 ; ($30) DDRD ds 1 ; PORTD ds 1 ; PINC ds 1 ; DDRC ds 1 ; PORTC ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; ds 1 ; ds 1 ; ds 1 ; EECR ds 1 ; EEDR ds 1 ; EEARL ds 1 ; EEARH ds 1 ; UCSR0C ds 1 ; ($40) UBRR0H equ UCSR0C ; ($40) WDTCR ds 1 ; ASSR ds 1 ; OCR2 ds 1 ; TCNT2 ds 1 ; TCCR2 ds 1 ; ICR1L ds 1 ; ICR1H ds 1 ; OCR1BL ds 1 ; OCR1BH ds 1 ; OCR1AL ds 1 ; OCR1AH ds 1 ; TCNT1L ds 1 ; TCNT1H ds 1 ; TCCR1B ds 1 ; TCCR1A ds 1 ; SFIOR ds 1 ; ($50) OSCCAL ds 1 ; TCNT0 ds 1 ; TCCR0 ds 1 ; MCUCSR ds 1 ; MCUCR ds 1 ; TWCR ds 1 ; SPMCR ds 1 ; TIFR ds 1 ; TIMSK ds 1 ; GIFR ds 1 ; GICR ds 1 ; ds 1 ; SPL ds 1 ; SPH ds 1 ; SREG ds 1 ; ; IRQ enable bits, etc UNCHECKED !!! ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK bOCIE0 =$02 ; In TIMSK ; Flags bOCF0 =$02 ; In TIFR bTOV0 =$01 ; ; Timer 1 enable bits bTOIE1 =$04 ; In TIMSK bOCIE1B =$08 ; In TIMSK bOCIE1A =$10 ; In TIMSK bTICIE1 =$20 ; In TIMSK bOCIE1C =$01 ; In ETIMSK ; Flags bTOV1 =$02 ; In TIFR bOFC1B =$04 ; In TIFR bOFC1A =$08 ; In TIFR bIFC1 =$10 ; In TIFR ; Timer 2 enable bits bTOIE2 =$40 ; In TIMSK bOCIE2 =$80 ; In TIMSK ; Flags bTOV2 =$40 ; In TIFR bOCF2 =$80 ; In TIFR ; Timer 3 enable bits bOCIE3C =$02 ; In ETIMSK bTOIE3 =$04 ; In ETIMSK bOCIE3B =$08 ; In ETIMSK bOCIE3A =$10 ; In ETIMSK bTICIE3 =$20 ; In ETIMSK ; Comm enable bits bTXEN = $08 ; In UCSRxB bRXEN = $10 ; In UCSRxB bUDRIE = $20 ; In UCSRxB bTXCIE = $40 ; In UCSRxB bRXCIE = $80 ; In UCSRxB al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $400 ; Size of SRAM EEROMSIZE equ $200 ; Size of EEROM org $60 RAMSTART ds RAMSIZE ; Adjust for registers and I/O RAMEND equ *-1 ; Last byte FLASHLENGTH equ $2000 ; Size of FLASH FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. These are the new definitions of the fuse control. . . 10/12/2003 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and $0F) + ((fsSUT and $03)<<4) if not def fsBOD fsFuseLow = fsFuseLowT1 or $C0 ; High is disabled else ; We have a BOD. What level? if fsBOD=4 fsFuseLow = fsFuseLowT1 ; 4V else fsFuseLow = fsFuseLowT1 or $80 ; ~2V endif endif ; Fuse High fsFuseHighEn = 1 if def fsBOOT_HIGH fsFHT1 = %0 0 0 0 0 00 0 or ((fsBOOTSZ and $03)<<1) else fsFHT1 = %0 0 0 0 0 00 1 ; Don't boot endif if def fsEESAVE fsFHT2 = fsFHT1 else fsFHT2 = fsFHT1 or (1<<3) endif if fsCLKOPT fsFHT3 = fsFHT2 or (1<<4) else fsFHT3 = fsFHT2 endif if def fsWDTFORCE fsFHT4 = fsFHT3 or (1<<6) else fsFHT4 = fsFHT3 endif fsFuseHigh = fsFHT4 or $80 ; Can't disable RESET else fsFuseLowEn = 0 ; Don't drive the fuses fsFuseLow = 0 fsFuseHighEn = 0 fsFuseHigh = 0 endif ; We don't have an extended fuse byte fsFuseExtEn = 0 ; Turn these off by default fsFuseExt = 0 ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif ; Interrupt vectors org 0 RESETaddr ds 2 ; RESET INT0addr ds 2 ; External Interrupt0 Vector Address INT1addr ds 2 ; External Interrupt1 Vector Address TMR2CMPaddr ds 2 ; Timer 2 compare TMR2OVRaddr ds 2 ; Timer 2 Overflow TMR1CAPaddr ds 2 ; Timer 1 Capture TMR1COMPAaddr ds 2 ; Timer 1 Compare A TMR1COMPBaddr ds 2 ; Timer 1 Compare B TMR1OVRaddr ds 2 ; Timer 1 OVR TMR0OVRaddr ds 2 ; Timer 0 Overflow SPISTCaddr ds 2 ; SPI STC USART0_RXaddr ds 2 ; USART0 Rx complete USART0_UDREaddr ds 2 ; USART0 Data register empty USART0_TXaddr ds 2 ; USART0 Tx complete ADCaddr ds 2 ; ADC Conversion Complete EERDYaddr ds 2 ; EEROM Ready ANALOGaddr ds 2 ; Analog Comparator TWIaddr ds 2 ; Two wire serial SPMaddr ds 2 ; SPM Ready EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here rjmp vStart ; Reset Vector if def irqEI0 rjmp irqEI0 ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI1 rjmp irqEI1 ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2CMP rjmp irqTMR2CMP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2OVR rjmp irqTMR2OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1CAP rjmp irqTMR1CAP ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPA rjmp irqTMR1COMPA ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPB rjmp irqTMR1COMPB ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1OVR rjmp irqTMR1OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR rjmp irqTMR0OVR ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPISTC rjmp irqSPISTC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_RX rjmp irqUSART0_RX ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_UDRE rjmp irqUSART0_UDRE ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_TX rjmp irqUSART0_TX ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqADC rjmp irqADC ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEERDY rjmp irqEERDY ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANALOG rjmp irqANALOG ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTWI rjmp irqTWI ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPM rjmp irqSPM ; Use the defined one else rjmp virqSpurious ; External Interrupt0 Vector Address endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtMega8 ; AtMega16 if CPU_NAME ="ATMEGA16" optDevTypeByte = $08 ; Device ID for the programmer ; ***** I/O Register Definitions UNTESTED!! org $20 ; IO port addressing mode setiooffset $20 ; This subtracts $20 from addresses in IO ; instructions. al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $400 ; Size of SRAM EEROMSIZE equ $200 ; Size of EEROM org $60 RAMSTART ds RAMSIZE ; Adjust for registers and I/O RAMEND equ *-1 ; Last byte FLASHLENGTH equ $2000 ; Size of FLASH FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH ; Device fuses. These are the new definitions of the fuse control. . . 10/12/2003 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and $0F) + ((fsSUT and $03)<<4) if not def fsBOD fsFuseLow = fsFuseLowT1 or $C0 ; High is disabled else ; We have a BOD. What level? if fsBOD=4 fsFuseLow = fsFuseLowT1 ; 4V else fsFuseLow = fsFuseLowT1 or $80 ; ~2V endif endif ; Fuse High fsFuseHighEn = 1 if def fsBOOT_HIGH fsFHT1 = %0 0 0 0 0 00 0 or ((fsBOOTSZ and $03)<<1) else fsFHT1 = %0 0 0 0 0 00 1 ; Don't boot endif if def fsEESAVE fsFHT2 = fsFHT1 else fsFHT2 = fsFHT1 or (1<<3) endif if fsCLKOPT fsFHT3 = fsFHT2 or (1<<4) else fsFHT3 = fsFHT2 endif if def fsJTAGEN fsFHT4 = fsFHT3 else fsFHT4 = fsFHT3 or (1<<6) ; Disable endif if def fsOCDEN fsFHT5 = fsFHT4 else fsFHT5 = fsFHT4 or (1<<7) ; Disable endif fsFuseHigh = fsFHT5 else fsFuseLowEn = 0 ; Don't drive the fuses fsFuseLow = 0 fsFuseHighEn = 0 fsFuseHigh = 0 endif ; We don't have an extended fuse byte fsFuseExtEn = 0 ; Turn these off by default fsFuseExt = 0 ; Allow access to the lock bits if def fsLockByte fsFuseLockEn = 1 fsFuseLock = fsLockByte else fsFuseLockEn = 0 fsFuseLock = $ff endif ; Interrupt vectors org 0 RESETaddr ds 4 ; RESET INT0addr ds 4 ; External Interrupt0 Vector Address INT1addr ds 4 ; External Interrupt1 Vector Address TMR2CMPaddr ds 4 ; Timer 2 compare TMR2OVRaddr ds 4 ; Timer 2 Overflow TMR1CAPaddr ds 4 ; Timer 1 Capture TMR1COMPAaddr ds 4 ; Timer 1 Compare A TMR1COMPBaddr ds 4 ; Timer 1 Compare B TMR1OVRaddr ds 4 ; Timer 1 OVR TMR0OVRaddr ds 4 ; Timer 0 Overflow SPISTCaddr ds 4 ; SPI STC USART0_RXaddr ds 4 ; USART0 Rx complete USART0_UDREaddr ds 4 ; USART0 Data register empty USART0_TXaddr ds 4 ; USART0 Tx complete ADCaddr ds 4 ; ADC Conversion Complete EERDYaddr ds 4 ; EEROM Ready ANALOGaddr ds 4 ; Analog Comparator TWIaddr ds 4 ; Two wire serial INT2addr ds 4 ; External Interrupt2 Vector Address TMR0COMPaddr ds 4 ; Timer 0 Compare SPMaddr ds 4 ; SPM Ready EOIVaddr equ * ; End of vectors ; Move back to start org 0 ; Start here jmp vStart ; Reset Vector if def irqEI0 jmp irqEI0 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI1 jmp irqEI1 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2CMP jmp irqTMR2CMP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2OVR jmp irqTMR2OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1CAP jmp irqTMR1CAP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPA jmp irqTMR1COMPA ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPB jmp irqTMR1COMPB ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1OVR jmp irqTMR1OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR jmp irqTMR0OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPISTC jmp irqSPISTC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_RX jmp irqUSART0_RX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_UDRE jmp irqUSART0_UDRE ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_TX jmp irqUSART0_TX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqADC jmp irqADC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEERDY jmp irqEERDY ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANALOG jmp irqANALOG ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTWI jmp irqTWI ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI2 jmp irqEI2 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0COMP jmp irqTMR0COMP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPM jmp irqSPM ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if EOIVaddr <> * zeuserror "Error in IRQ vectors" endif endif ; End of AtMega16 ; At90S233 or At90S4433 if (CPU_NAME ="AT2333") or (CPU_NAME ="AT4433") setiooffset $00 ; For compatibility ; ***** I/O Register Definitions SREG = $3f SPL = $3d GIMSK = $3b TIMSK = $39 TIFR = $38 MCUCR = $35 MCUSR = $34 TCCR0 = $33 TCNT0 = $32 TCCR1A = $2f TCCR1B = $2e TCNT1H = $2d TCNT1L = $2c OCR1H = $2b OCR1L = $2a ICR1H = $27 ICR1L = $26 WDTCR = $21 EEAR = $1e EEDR = $1d EECR = $1c PORTB = $18 DDRB = $17 PINB = $16 PORTC = $15 DDRC = $14 PINC = $13 PORTD = $12 DDRD = $11 PIND = $10 SPDR = $0f SPSR = $0e SPCR = $0d UDR = $0c USR = $0b UCR = $0a UBRRL = $09 UBRRH = $03 ACSR = $08 ADMUX = $07 ADCSR = $06 ADCH = $05 ADCL = $04 ;***** Bit Definitions WDRF = 3 ; Reset flags, bit positions BORF = 2 ; EXTRF = 1 ; PORF = 0 ; INT1 = 7 ; Interrupt mask bits INT0 = 6 ; INTF1 = 7 ; Interrupt flag bits INTF0 = 6 ; TOIE1 = 7 ; TIMSK bits OCIE1 = 6 ; bOCIE1 = $40; TICI1 = 3 ; TOIE0 = 1 ; TOV1 = 7 ; TIFR OCF1 = 6 ; ICF1 = 3 ; TOV0 = 1 ; bTOV0 = $02; SE = 5 ; MCUCR SM = 4 ; ISC11 = 3 ; ISC10 = 2 ; ISC01 = 1 ; ISC00 = 0 ; CS02 = 2 ; TCCR0 CS01 = 1 ; CS00 = 0 ; COM11 = 7 ; TCCR1A COM10 = 6 ; PWM11 = 1 ; PWM10 = 0 ; ICNC1 = 7 ; TCCR1B ICES1 = 6 ; CTC1 = 3 ; CS12 = 2 ; CS11 = 1 ; CS10 = 0 ; WDTOE = 4 ; WDTCR WDE = 3 ; WDP2 = 2 ; WDP1 = 1 ; WDP0 = 0 ; EERIE = 3 ; EECR EEMWE = 2 ; EEWE = 1 ; EERE = 0 ; SPIE = 7 ; SPCR SPE = 6 ; DORD = 5 ; MSTR = 4 ; CPOL = 3 ; CPHA = 2 ; SPR1 = 1 ; SPR0 = 0 ; SPIF = 7 ; SPSR WCOL = 6 ; RXC = 7 ; UCSRA TXC = 6 ; UDRE = 5 ; FE = 4 ; Or = 3 ; MPCM = 0 ; RXCIE = 7 ; UCSRB TXCIE = 6 ; UDRIE = 5 ; RXEN = 4 ; TXEN = 3 ; CHR9 = 2 ; RXB8 = 1 ; TXB8 = 0 ; ACD = 7 ; ACSR AINBG = 6 ; ACO = 5 ; ACI = 4 ; ACIE = 3 ; ACIC = 2 ; ACIS1 = 1 ; ACIS0 = 0 ; ADCBG = 6 ; ADMUX MUX2 = 2 ; MUX1 = 1 ; MUX0 = 0 ; ADEN = 7 ; ADCSR ADSC = 6 ; ADFR = 5 ; ADIF = 4 ; ADIE = 3 ; ADPS2 = 2 ; ADPS1 = 1 ; ADPS0 = 0 ; al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; Resetaddr=$000 ;Reset Vector Address INT0addr=$001 ;External Interrupt0 Vector Address INT1addr=$002 ;External Interrupt1 Vector Address ICP1addr=$003 ;Timer1 Input Capture Vector Address OC1Aaddr=$004 ;Timer1 Output Compare A Interrupt Vector Address OVF1addr=$005 ;Overflow1 Interrupt Vector Address OVF0addr=$006 ;Overflow0 Interrupt Vector Address SPIaddr =$007 ;SPI Interrupt Vector Address URXCaddr=$008 ;UART Receive Complete Interrupt Vector Address UDREaddr=$009 ;UART Data Register Empty Interrupt Vector Address UTXCaddr=$00A ;UART Transmit Complete Interrupt Vector Address ADCCaddr=$00B ;ADC Conversion Complete Interrupt Vector Address ERDYaddr=$00C ;EEPROM Write Complete Interrupt Vector Address ACIaddr =$00D ;Analog Comparator Interrupt Vector Address RAMEND =$0DF ;Last On-Chip SRAM location XRAMEND =$0DF psFUSEBASE equ $FF00 ; The ParaSys Driver puts them here. . . ; Device fuses if def DriveFuses ; Fuse fsFuseEn = 1 fsFuseT1 = (fsCKSEL and $07) if fsBOD fsFuseT2 = fsFuseT1 ; Low = enabled else fsFuseT2 = fsFuseT1 or $08 ; Disable it endif if fsBODLevel fsFuse = fsFuseT2 or $C0; Low = 4V else fsFuse = fsFuseT2 or $10 or $C0; 2.7V endif else fsFuseEn = 0 ; Don't drive the fuses fsFuse = 0 endif if def LockFuses fsFuseLockEn = 1 fsFuseLock = LockFuses else fsFuseLockEn = 0 fsFuseLock = $ff endif org psFUSEBASE db fsFuseEn ; Fuse low db fsFuse ; db fsFuseLockEn ; Lock fuses db fsFuseLock ; endif if CPU_NAME ="AT2333" optDevTypeByte = $01 ; Device ID for the programmer E2END =$07F ; 128 bytes EEROM FLASHEND=$3FF ; 1024 WORDS FLASH endif if CPU_NAME ="AT4433" optDevTypeByte = $02 ; Device ID for the programmer E2END =$0FF ; 256 bytes EEROM FLASHEND=$7FF ; 2048 WORDS FLASH endif if CPU_NAME ="AT8515" optDevTypeByte = $03 ; Device ID for the programmer setiooffset $00 ; For compatibility ; ***** I/O Register Definitions SREG = $3f SPH = $3e SPL = $3d GIMSK = $3b TIMSK = $39 TIFR = $38 MCUCR = $35 TCCR0 = $33 TCNT0 = $32 TCCR1A = $2f TCCR1B = $2e TCNT1H = $2d TCNT1L = $2c OCR1AH = $2b OCR1AL = $2a OCR1BH = $29 OCR1BL = $28 ICR1H = $25 ICR1L = $24 WDTCR = $21 EEARH = $1f EEARL = $1e EEDR = $1d EECR = $1c PORTA = $1b DDRA = $1a PINA = $19 PORTB = $18 DDRB = $17 PINB = $16 PORTC = $15 DDRC = $14 PINC = $13 PORTD = $12 DDRD = $11 PIND = $10 SPDR = $0f SPSR = $0e SPCR = $0d UDR = $0c USR = $0b UCR = $0a UBRR = $09 ACSR = $08 ; ***** Bit Definitions INT1 = 7 INT0 = 6 TOIE1 = 7 OCIE1A = 6 OCIE1B = 5 TICIE = 3 TOIE0 = 1 TOV1 = 7 bTOV1 = $80 OCF1A = 6 bOCF1A = $40 OCF1B = 5 ICF1 = 3 TOV0 = 1 bTOV0 = $02 SRE = 7 SRW = 6 SE = 5 SM = 4 ISC11 = 3 ISC10 = 2 ISC01 = 1 ISC00 = 0 CS02 = 2 CS01 = 1 CS00 = 0 COM1A1 = 7 COM1A0 = 6 COM1B1 = 5 COM1B0 = 4 PWM11 = 1 PWM10 = 0 ICNC1 = 7 ICES1 = 6 CTC1 = 3 CS12 = 2 CS11 = 1 CS10 = 0 WDE = 3 WDP2 = 2 WDP1 = 1 WDP0 = 0 EEAR8 = 0 EEWE = 1 EERE = 0 PA7 = 7 PA6 = 6 PA5 = 5 PA4 = 4 PA3 = 3 PA2 = 2 PA1 = 1 PA0 = 0 DDA7 = 7 DDA6 = 6 DDA5 = 5 DDA4 = 4 DDA3 = 3 DDA2 = 2 DDA1 = 1 DDA0 = 0 PINA7 = 7 PINA6 = 6 PINA5 = 5 PINA4 = 4 PINA3 = 3 PINA2 = 2 PINA1 = 1 PINA0 = 0 PB7 = 7 PB6 = 6 PB5 = 5 PB4 = 4 PB3 = 3 PB2 = 2 PB1 = 1 PB0 = 0 DDB7 = 7 DDB6 = 6 DDB5 = 5 DDB4 = 4 DDB3 = 3 DDB2 = 2 DDB1 = 1 DDB0 = 0 PINB7 = 7 PINB6 = 6 PINB5 = 5 PINB4 = 4 PINB3 = 3 PINB2 = 2 PINB1 = 1 PINB0 = 0 PC7 = 7 PC6 = 6 PC5 = 5 PC4 = 4 PC3 = 3 PC2 = 2 PC1 = 1 PC0 = 0 DDC7 = 7 DDC6 = 6 DDC5 = 5 DDC4 = 4 DDC3 = 3 DDC2 = 2 DDC1 = 1 DDC0 = 0 PINC7 = 7 PINC6 = 6 PINC5 = 5 PINC4 = 4 PINC3 = 3 PINC2 = 2 PINC1 = 1 PINC0 = 0 PD6 = 6 PD5 = 5 PD4 = 4 PD3 = 3 PD2 = 2 PD1 = 1 PD0 = 0 DDD6 = 6 DDD5 = 5 DDD4 = 4 DDD3 = 3 DDD2 = 2 DDD1 = 1 DDD0 = 0 PIND6 = 6 PIND5 = 5 PIND4 = 4 PIND3 = 3 PIND2 = 2 PIND1 = 1 PIND0 = 0 SPIF = 7 WCOL = 6 SPIE = 7 SPE = 6 DORD = 5 MSTR = 4 CPOL = 3 CPHA = 2 SPR1 = 1 SPR0 = 0 RXC = 7 TXC = 6 UDRE = 5 FE = 4 ;or = 3 RXCIE = 7 TXCIE = 6 UDRIE = 5 RXEN = 4 TXEN = 3 CHR9 = 2 RXB8 = 1 TXB8 = 0 ACD = 7 ACO = 5 ACI = 4 ACIE = 3 ACIC = 2 ACIS1 = 1 ACIS0 = 0 al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; RAMEND = $20 + $40 + $1ff ;Adjust for registers and I/O ; Modified for BYTE addressing INT0addr = $001 * 2 ;External Interrupt0 Vector Address INT1addr = $002 * 2 ;External Interrupt1 Vector Address ICP1addr = $003 * 2 ;Input Capture1 Interrupt Vector Address OC1Aaddr = $004 * 2 ;Output Compare1A Interrupt Vector Address OC1Baddr = $005 * 2 ;Output Compare1B Interrupt Vector Address OVF1addr = $006 * 2 ;Overflow1 Interrupt Vector Address OC0addr = $007 * 2 ;Output Compare0 Interrupt Vector Address OVF0addr = $008 * 2 ;Overflow0 Interrupt Vector Address SPIaddr = $009 * 2 ;SPI Interrupt Vector Address URXCaddr = $00a * 2 ;UART Receive Complete Interrupt Vector Address UDREaddr = $00b * 2 ;UART Data Register Empty Interrupt Vector Address UTXCaddr = $00c * 2 ;UART Transmit Complete Interrupt Vector Address ACIaddr = $00d * 2 ;Analog Comparator Interrupt Vector Address endif if CPU_NAME ="AT8535" optDevTypeByte = $04 ; Device ID for the programmer setiooffset $00 ; For compatibility ;***** Specify Device AT90S8535 = true ;***** I/O Register Definitions SREG =$3f SPH =$3e SPL =$3d GIMSK =$3b GIFR =$3a TIMSK =$39 TIFR =$38 MCUCR =$35 MCUSR =$34 TCCR0 =$33 TCNT0 =$32 TCCR1A =$2f TCCR1B =$2e TCNT1H =$2d TCNT1L =$2c OCR1AH =$2b OCR1AL =$2a OCR1BH =$29 OCR1BL =$28 ICR1H =$27 ICR1L =$26 TCCR2 =$25 TCNT2 =$24 OCR2 =$23 ASSR =$22 WDTCR =$21 EEARH =$1f EEARL =$1e EEDR =$1d EECR =$1c PORTA =$1b DDRA =$1a PINA =$19 PORTB =$18 DDRB =$17 PINB =$16 PORTC =$15 DDRC =$14 PINC =$13 PORTD =$12 DDRD =$11 PIND =$10 SPDR =$0f SPSR =$0e SPCR =$0d UDR =$0c USR =$0b UCR =$0a UBRR =$09 ACSR =$08 ADMUX =$07 ADCSR =$06 ADCH =$05 ADCL =$04 ;***** Bit Definitions EXTRF =1 PORF =0 INT1 =7 INT0 =6 INTF1 =7 INTF0 =6 OCIE2 =7 TOIE2 =6 TICIE1 =5 OCIE1A =4 OCIE1B =3 TOIE1 =2 TOIE0 =0 OCF2 =7 TOV2 =6 ICF1 =5 OCF1A =4 bOCF1A =$10 OCF1B =3 bOCF1B =$08 TOV1 =2 bTOV1 =$02 TOV0 =0 bTOV0 =$01 SE =6 SM1 =5 SM0 =4 ISC11 =3 ISC10 =2 ISC01 =1 ISC00 =0 CS02 =2 CS01 =1 CS00 =0 COM1A1 =7 COM1A0 =6 COM1B1 =5 COM1B0 =4 PWM11 =1 PWM10 =0 ICNC1 =7 ICES1 =6 CTC1 =3 CS12 =2 CS11 =1 CS10 =0 PWM2 =6 COM21 =5 COM20 =4 CTC2 =3 CS22 =2 CS21 =1 CS20 =0 AS2 =3 TCN2UB =2 OCR2UB =1 TCR2UB =0 WDDE =4 WDE =3 WDP2 =2 WDP1 =1 WDP0 =0 EERIE =3 EEMWE =2 EEWE =1 EERE =0 SPIE =7 SPE =6 DORD =5 MSTR =4 CPOL =3 CPHA =2 SPR1 =1 SPR0 =0 SPIF =7 WCOL =6 RXC =7 TXC =6 UDRE =5 FE =4 Or =3 RXCIE =7 TXCIE =6 UDRIE =5 RXEN =4 TXEN =3 CHR9 =2 RXB8 =1 TXB8 =0 ACD =7 ACO =5 ACI =4 ACIE =3 ACIC =2 ACIS1 =1 ACIS0 =0 MUX2 =2 MUX1 =1 MUX0 =0 ADEN =7 ADSC =6 ADFR =5 ADIF =4 ADIE =3 ADPS2 =2 ADPS1 =1 ADPS0 =0 al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; RAMEND =$25F ;Last On-Chip SRAM location XRAMEND =$25F E2END =$1FF FLASHEND=$FFF INT0addr=$001 ;External Interrupt0 Vector Address INT1addr=$002 ;External Interrupt1 Vector Address OC2addr =$003 ;Timer2 compare match Vector Address OVF2addr=$004 ;Timer2 overflow Vector Address ICP1addr=$005 ;Timer1 Input Capture Vector Address OC1Aaddr=$006 ;Timer1 Output Compare A Interrupt Vector Address OC1Baddr=$007 ;Timer1 Output Compare B Interrupt Vector Address OVF1addr=$008 ;Overflow1 Interrupt Vector Address OVF0addr=$009 ;Overflow0 Interrupt Vector Address SPIaddr =$00A ;SPI Interrupt Vector Address URXCaddr=$00B ;UART Receive Complete Interrupt Vector Address UDREaddr=$00C ;UART Data Register Empty Interrupt Vector Address UTXCaddr=$00D ;UART Transmit Complete Interrupt Vector Address ADCCaddr=$00E ;ADC Conversion Complete Interrupt Vector Address ERDYaddr=$00F ;EEPROM Write Complete Interrupt Vector Address ACIaddr =$010 ;Analog Comparator Interrupt Vector Address endif if (CPU_NAME ="ATMEGA64") or (CPU_NAME ="ATMEGA128") if CPU_NAME ="ATMEGA64" optDevTypeByte = $0F ; Device ID for the programmer else optDevTypeByte = $0A ; Device ID for the programmer endif ; ***** I/O Register Definitions org $20 ; IO port addressing mode setiooffset $20 ; This subtracts $20 from addresses in IO ; instructions. PINF ds 1 ; ($20) PINE ds 1 ; DDRE ds 1 ; PORTE ds 1 ; ADCL ds 1 ; ADCH ds 1 ; ADCSRA ds 1 ; ADMUX ds 1 ; ACSR ds 1 ; UBRR0L ds 1 ; UCSR0B ds 1 ; UCSR0A ds 1 ; UDR0 ds 1 ; SPCR ds 1 ; SPSR ds 1 ; SPDR ds 1 ; PIND ds 1 ; ($30) DDRD ds 1 ; PORTD ds 1 ; PINC ds 1 ; DDRC ds 1 ; PORTC ds 1 ; PINB ds 1 ; DDRB ds 1 ; PORTB ds 1 ; PINA ds 1 ; DDRA ds 1 ; PORTA ds 1 ; EECR ds 1 ; EEDR ds 1 ; EEARL ds 1 ; EEARH ds 1 ; SFIOR ds 1 ; ($40) WDTCR ds 1 ; OCDR ds 1 ; OCR2 ds 1 ; TCNT2 ds 1 ; TCCR2 ds 1 ; ICR1L ds 1 ; ICR1H ds 1 ; OCR1BL ds 1 ; OCR1BH ds 1 ; OCR1AL ds 1 ; OCR1AH ds 1 ; TCNT1L ds 1 ; TCNT1H ds 1 ; TCCR1B ds 1 ; TCCR1A ds 1 ; ASSR ds 1 ; ($50) OCR0 ds 1 ; TCNT0 ds 1 ; TCCR0 ds 1 ; MCUCSR ds 1 ; MCUCR ds 1 ; TIFR ds 1 ; TIMSK ds 1 ; EIFR ds 1 ; EIMSK ds 1 ; EICRB ds 1 ; RAMPZ ds 1 ; XDIV ds 1 ; SPL ds 1 ; SPH ds 1 ; SREG ds 1 ; ds 1 ; ($60) DDRF ds 1 ; PORTF ds 1 ; PING ds 1 ; DDRG ds 1 ; PORTG ds 1 ; ds 1 ; ds 1 ; SPMCSR ds 1 ; ds 1 ; EICRA ds 1 ; ds 1 ; XMCRB ds 1 ; XMCRA ds 1 ; ds 1 ; OSCCAL ds 1 ; TWBR ds 1 ; ($70) TWSR ds 1 ; TWAR ds 1 ; TWDR ds 1 ; TWCR ds 1 ; ds 1 ; ds 1 ; ds 1 ; OCR1CL ds 1 ; OCR1CH ds 1 ; TCCR1C ds 1 ; ds 1 ; ETIFR ds 1 ; ETIMSK ds 1 ; ds 1 ; ds 1 ; ICR3L ds 1 ; ($80) ICR3H ds 1 ; OCR3CL ds 1 ; OCR3CH ds 1 ; OCR3BL ds 1 ; OCR3BH ds 1 ; OCR3AL ds 1 ; OCR3AH ds 1 ; TCNT3L ds 1 ; TCNT3H ds 1 ; TCCR3B ds 1 ; TCCR3A ds 1 ; TCCR3C ds 1 ; ds 1 ; ds 1 ; ds 1 ; UBRR0H ds 1 ; ($90) ds 1 ; ds 1 ; ds 1 ; ds 1 ; UCSR0C ds 1 ; ds 1 ; ds 1 ; UBRR1H ds 1 ; UBRR1L ds 1 ; UCSR1B ds 1 ; UCSR1A ds 1 ; UDR1 ds 1 ; UCSR1C ds 1 ; ; IRQ enable bits, etc ; Timer 0 enable bits bTOIE0 =$01 ; In TIMSK bOCIE0 =$02 ; In TIMSK ; Flags bOCF0 =$02 ; In TIFR bTOV0 =$01 ; ; Timer 1 enable bits bTOIE1 =$04 ; In TIMSK bOCIE1B =$08 ; In TIMSK bOCIE1A =$10 ; In TIMSK bTICIE1 =$20 ; In TIMSK bOCIE1C =$01 ; In ETIMSK ; Flags bTOV1 =$02 ; In TIFR bOFC1B =$04 ; In TIFR bOFC1A =$08 ; In TIFR bIFC1 =$10 ; In TIFR ; Timer 2 enable bits bTOIE2 =$40 ; In TIMSK bOCIE2 =$80 ; In TIMSK ; Flags bTOV2 =$40 ; In TIFR bOCF2 =$80 ; In TIFR ; Timer 3 enable bits bOCIE3C =$02 ; In ETIMSK bTOIE3 =$04 ; In ETIMSK bOCIE3B =$08 ; In ETIMSK bOCIE3A =$10 ; In ETIMSK bTICIE3 =$20 ; In ETIMSK ; Comm enable bits bTXEN = $08 ; In UCSRxB bRXEN = $10 ; In UCSRxB bUDRIE = $20 ; In UCSRxB bTXCIE = $40 ; In UCSRxB bRXCIE = $80 ; In UCSRxB al reg r16 ; My convention for register names ah reg r17 ; bl reg r18 ; bh reg r19 ; cl reg r20 ; ch reg r21 ; rll reg r22 ; rlh reg r23 ; rhl reg r24 ; rhh reg r25 ; xl reg r26 ; ATMEL's convention for register names xh reg r27 ; yl reg r28 ; yh reg r29 ; zl reg r30 ; zh reg r31 ; RAMSIZE equ $1000 ; Size of SRAM org $100 RAMSTART ds RAMSIZE ; Adjust for registers and I/O RAMEND equ *-1 ; Last byte if CPU_NAME ="ATMEGA64" FLASHLENGTH equ $10000 ; Size of FLASH EEROMSIZE equ $800 ; Size of EEROM elseif CPU_NAME ="ATMEGA128" FLASHLENGTH equ $20000 ; Size of FLASH EEROMSIZE equ $1000 ; Size of EEROM endif FLASHEND equ FLASHLENGTH-1 ; Last byte of FLASH psEEROMBASE equ $100000 ; The ParaSys Driver puts it here. . . psFUSEBASE equ $200000 ; The ParaSys Driver puts them here. . . ; Device fuses. These are the new definitions of the fuse control. . . 10/12/2003 if def DriveFuses ; Fuse Low fsFuseLowEn = 1 fsFuseLowT1 = (fsClockSrc and $0F) + ((fsSUT and $03)<<4) if not def fsBOD fsFuseLow = fsFuseLowT1 or $C0 ; High is disabled else ; We have a BOD. What level? if fsBOD=4 fsFuseLow = fsFuseLowT1 ; 4V else fsFuseLow = fsFuseLowT1 or $80 ; ~2V endif endif ; Fuse High fsFuseHighEn = 1 if CPU_NAME ="ATMEGA64" if def fsBOOT_HIGH fsFHT1 = %0 0 0 0 0 00 0 or ((fsBOOTSZ and $03)<<1) if fsBOOTSZ = 0 Vector_Base_B equ $E000 elseif fsBOOTSZ = 1 Vector_Base_B equ $F000 elseif fsBOOTSZ = 2 Vector_Base_B equ $F800 elseif fsBOOTSZ = 3 Vector_Base_B equ $FC00 endif else fsFHT1 = %0 0 0 0 0 00 1 ; Don't boot Vector_Base_B equ 0 endif elseif CPU_NAME ="ATMEGA128" if def fsBOOT_HIGH fsFHT1 = %0 0 0 0 0 00 0 or ((fsBOOTSZ and $03)<<1) if fsBOOTSZ = 0 Vector_Base_B equ $1E000 elseif fsBOOTSZ = 1 Vector_Base_B equ $1F000 elseif fsBOOTSZ = 2 Vector_Base_B equ $1F800 elseif fsBOOTSZ = 3 Vector_Base_B equ $1FC00 endif else fsFHT1 = %0 0 0 0 0 00 1 ; Don't boot Vector_Base_B equ 0 endif endif ; Now, we might want to put the code low but boot high if def fsVECTORS_LOW Vector_Base equ 0 else Vector_Base equ Vector_Base_B endif if def fsEESAVE fsFHT2 = fsFHT1 else fsFHT2 = fsFHT1 or (1<<3) endif if fsCLKOPT fsFHT3 = fsFHT2 or (1<<4) else fsFHT3 = fsFHT2 endif if def fsJTAGEN fsFHT4 = fsFHT3 else fsFHT4 = fsFHT3 or (1<<6) ; Disable endif if def fsOCDEN fsFHT5 = fsFHT4 else fsFHT5 = fsFHT4 or (1<<7) ; Disable endif fsFuseHigh = fsFHT5 ; Fuse Extended fsFuseExtEn = 1 if def fsWDTFORCE fsFE1 = $FE else fsFE1 = $FF endif if def fsM103C fsFuseExt = fsFE1 and $FD else fsFuseExt = fsFE1 endif else fsFuseLowEn = 0 ; Don't drive the fuses fsFuseLow = 0 fsFuseHighEn = 0 fsFuseHigh = 0 fsFuseExtEn = 0 fsFuseExt = 0 endif if def LockFuses fsFuseLockEn = 1 fsFuseLock = LockFuses else fsFuseLockEn = 0 fsFuseLock = $ff endif org psFUSEBASE db fsFuseLowEn ; Fuse low db fsFuseLow ; db fsFuseHighEn ; Fuse high db fsFuseHigh ; db fsFuseExtEn ; Fuse extended db fsFuseExt ; db fsFuseLockEn ; Lock fuses db fsFuseLock ; ; Interrupt vectors org Vector_Base RESETaddr ds 4 ; RESET INT0addr ds 4 ; External Interrupt0 Vector Address INT1addr ds 4 ; External Interrupt1 Vector Address INT2addr ds 4 ; External Interrupt2 Vector Address INT3addr ds 4 ; External Interrupt3 Vector Address INT4addr ds 4 ; External Interrupt4 Vector Address INT5addr ds 4 ; External Interrupt5 Vector Address INT6addr ds 4 ; External Interrupt6 Vector Address INT7addr ds 4 ; External Interrupt7 Vector Address TMR2CMPaddr ds 4 ; Timer 2 compare TMR2OVRaddr ds 4 ; Timer 2 Overflow TMR1CAPaddr ds 4 ; Timer 1 Capture TMR1COMPAaddr ds 4 ; Timer 1 Compare A TMR1COMPBaddr ds 4 ; Timer 1 Compare B TMR1OVRaddr ds 4 ; Timer 1 OVR TMR0COMPaddr ds 4 ; Timer 0 Compare TMR0OVRaddr ds 4 ; Timer 0 Overflow SPISTCaddr ds 4 ; SPI STC USART0_RXaddr ds 4 ; USART0 Rx complete USART0_UDREaddr ds 4 ; USART0 Data register empty USART0_TXaddr ds 4 ; USART0 Tx complete ADCaddr ds 4 ; ADC Conversion Complete EERDYaddr ds 4 ; EEROM Ready ANALOGaddr ds 4 ; Analog Comparator TMR1COMPCaddr ds 4 ; Timer 1 Compare C TMR3CAPaddr ds 4 ; Timer 3 Capture TMR3COMPAaddr ds 4 ; Timer 3 Compare A TMR3COMPBaddr ds 4 ; Timer 3 Compare B TMR3COMPCaddr ds 4 ; Timer 3 Compare C TMR3OVRaddr ds 4 ; Timer 3 OVR USART1_RXaddr ds 4 ; USART1 Rx complete USART1_UDREaddr ds 4 ; USART1 Data register empty USART1_TXaddr ds 4 ; USART1 Tx complete TWIaddr ds 4 ; Two wire serial SPMaddr ds 4 ; SPM Ready EOIVaddr equ * ; End of vectors ; Move back to start org Vector_Base ; Start here jmp vStart ; Reset Vector if def irqEI0 jmp irqEI0 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI1 jmp irqEI1 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI2 jmp irqEI2 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI3 jmp irqEI3 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI4 jmp irqEI4 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI5 jmp irqEI5 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI6 jmp irqEI6 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEI7 jmp irqEI7 ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2CMP jmp irqTMR2CMP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR2OVR jmp irqTMR2OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1CAP jmp irqTMR1CAP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPA jmp irqTMR1COMPA ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPB jmp irqTMR1COMPB ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1OVR jmp irqTMR1OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0COMP jmp irqTMR0COMP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR0OVR jmp irqTMR0OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPISTC jmp irqSPISTC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_RX jmp irqUSART0_RX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_UDRE jmp irqUSART0_UDRE ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART0_TX jmp irqUSART0_TX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqADC jmp irqADC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqEERDY jmp irqEERDY ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqANALOG jmp irqANALOG ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR1COMPC jmp irqTMR1COMPC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR3CAP jmp irqTMR3CAP ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR3COMPA jmp irqTMR3COMPA ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR3COMPB jmp irqTMR3COMPB ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR3COMPC jmp irqTMR3COMPC ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTMR3OVR jmp irqTMR3OVR ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART1_RX jmp irqUSART1_RX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART1_UDRE jmp irqUSART1_UDRE ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqUSART1_TX jmp irqUSART1_TX ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqTWI jmp irqTWI ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif if def irqSPM jmp irqSPM ; Use the defined one else jmp virqSpurious ; External Interrupt0 Vector Address endif ; if EOIVaddr <> * ; zeusprint "Error in IRQ vectors" ; endif endif ; Baud-rate and other timing related bits, common to all CPU's if def CPU_Clk if CPU_Clk = 3686400 b57600 equ 3 ; = 57600 @ 3.6MHz clock b19200 equ 11 ; = 19200 @ 3.6MHz clock b9600 equ 23 ; = 9600 @ 3.6MHz clock endif if CPU_Clk = 4000000 b19200 equ 12 ; = 19200 @ 4.0MHz clock b9600 equ 25 ; = 9600 @ 4.0MHz clock endif if CPU_Clk = 8000000 b57600 equ 8 ; = 57600 @ 8.0MHz clock b19200 equ 25 ; = 19200 @ 8.0MHz clock b9600 equ 51 ; = 9600 @ 8.0MHz clock endif if CPU_Clk = 16000000 b57600 equ 16 ; = 57600 @ 16.0MHz clock b19200 equ 51 ; = 19200 @ 16.0MHz clock b9600 equ 103 ; = 9600 @ 16.0MHz clock b4800 equ 207 ; = 4800 @ 16.0MHz clock b2400 equ 416 ; = 2400 @ 16.0MHz clock endif endif ; Now, we set the various driver options org psFUSEBASE if def fsFuseLow db fsFuseLowEn ; Fuse low db fsFuseLow ; else db 0,0 endif if def fsFuseHigh db fsFuseHighEn ; Fuse high db fsFuseHigh ; else db 0,0 endif if def fsFuseExt db fsFuseExtEn ; Fuse extended db fsFuseExt ; else db 0,0 endif if def fsFuseLock db fsFuseLockEn ; Lock fuses db fsFuseLock ; else db 0,0 endif org psOPTIONBASE ; Set the PSU voltage if def optVoltage df optVoltage ; Set the voltage else df 3.3 ; Set the voltage to 3.3V endif ; Set the Programming speed if def optProgSpeed db optProgSpeed ; Set the programming speed else db $0C ; ~1MHz endif ; Set the automatic EEROM writing flag if def optWriteEEROM db optWriteEEROM; Write or not. else db 0 ; Don't write endif ; Set the calibration fuse byte copy flag if (def optCopyCalByte) or (def optCopyCalLD) if (def optCopyCalByte) and (def optCopyCalLD) zeuserror "Can't use both options" endif if (def optCopyCalByte) db 1 ; Mode=Copy a byte db optCopyCalFuse ; Select which fuse to copy dl optCalByteAddr ; Set the address for it else db 2 ; Mode = Create a LD AL,#$nn db optCopyCalFuse ; Select which fuse to copy dl optCalByteAddr ; Set the address for it endif else db 0 ; Don't write db 0 ; Fuse 0 dl psOPTIONBASE-1 ; And don't put it anywhere if you do endif org psOPTIONBASE + $10 ; Set the device-type if def optDevTypeByte db optDevTypeByte; Set the device else db $00 ; [null] endif org psOPTIONBASE + $20 ; Set the Flash Size if def optProgFlashSize dl optProgFlashSize ; Set the device endif org psOPTIONBASE + $24 ; Set the EEROM Size if def optProgEEROMSize dl optProgEEROMSize ; Set the device endif if def EOIVaddr org EOIVaddr endif